Field effect transistors (FETs) are attractive as switching devices in power supplies. However, the high dv/dt stresses to which the switching devices in such power supplies are exposed can cause an internal body diode of a FET to conduct under normal power supply operating conditions. This internal body diode is a bipolar diode that stores an associated charge that can be relatively large because of the relatively large volume of the drift region in a power FET. Consequently, the recovery time of this diode after forward conduction can become a substantial portion of an operating cycle as the operating frequency is increased. The conduction in these diodes limits the maximum switching speed and contributes to power losses within the power supply.
One solution to this problem is to provide a Schottky diode in parallel with a FET. In a circuit including these elements, the body diode of the FET does not turn on if the Schottky diode has lower turn-on voltage than the turn-on voltage of the body diode. A fast reverse recovery results since Schottky diodes have very short reverse recovery times.
Reliably fabricating integrated circuits with FETs and Schottky diodes is difficult due to the formation of contaminants during processing. Contaminants formed during processing can deposit on a surface of an electrically conducting region that will form a Schottky contact. The electrically conducting region may be, for example, a semiconducting portion of a Schottky diode. If contaminants deposit on the electrically conducting layer, the conductivity at the surface of the electrically conducting region is altered. When a Schottky metal is deposited on the surface of the electrically conducting region, the formed Schottky diode may not function in its intended manner because of the altered conductivity of the electrically conducting region.
The contaminants that deposit on the electrically conducting regions can be produced at many stages of the fabrication process. For instance, contaminants may be produced during a photolithography process. Photolithography processes are used to form dielectric structures that isolate gate electrodes from source regions in FETs. In an exemplary process, a dielectric layer is first deposited on a semiconductor substrate. A layer of photoresist is then deposited on the dielectric layer and is irradiated with a pattern of radiation. The irradiated portions of the photoresist layer may be removed to form a photoresist pattern. Portions of the dielectric layer exposed through the photoresist pattern may be etched. After etching, the photoresist pattern may be stripped in a stripping chamber to leave a plurality of dielectric structures. During stripping, some of the photoresist may not be completely removed from the stripping chamber and can deposit on electrically conducting regions on the semiconductor substrate.
Contaminants can also be present in the air of a cleanroom or in processing fluids such as process gases and process liquids. Contaminants in the air or in processing fluids can also deposit on electrically conducting regions on a semiconductor substrate, thus altering the conductive properties of the electrically conducting regions.
Contaminants can also be produced in a reflow process. FIG. 1, for example, shows a semiconductor substrate 202 having a plurality of trench metal oxide field effect transistor (MOSFET) devices 200 and a plurality of electrically conducting regions 218 comprising a semiconducting material. Dielectric structures 250 made of BPSG (borophosphosilicate glass) are disposed on the semiconductor substrate 202 and isolate the gate electrodes from the source regions in the MOSFET devices 200. In this example, the electrically conducting regions 218 have an upper surface that coincides with the upper surface of the semiconductor substrate 202. The electrically conducting regions 218 are disposed to the sides of the dielectric structures 250.
During a reflow process, the dielectric structures 250 are heated to melt them. When the dielectric structures 250 are heated, dopants such as boron and phosphorous in the dielectric structures 250 vaporize and deposit on and/or diffuse into electrically conducting regions 218 on the semiconductor substrate 202. This is sometimes referred to as xe2x80x9cautodopingxe2x80x9d. As shown by the arrows 150 in FIG. 1, in autodoping, dopants can deposit anywhere on the semiconductor substrate 202. Dopants that are at the electrically conducting regions 218 alter the surface conductivity of the electrically conducting regions 218. When a conductive material (not shown) such as a Schottky metal is deposited on the electrically conducting regions 218, a Schottky diode is formed. Because of the altered conductivity of the electrically conducting regions 218, the formed Schottky diode may not function as intended.
In sum, the presence of contaminants at electrically conducting regions on a semiconductor substrate makes reliable volume production of devices such as Schottky diodes difficult. Embodiments of the invention address these and other problems.
Embodiments of the invention relate to methods for removing contaminants from electrically conducting regions that are disposed adjacent a dielectric structure. Broadly, contaminants at the electrically conducting regions can be removed by, for example, etching a portion of the electrically conducting regions.
One embodiment of the invention is directed to a method for removing contaminants on a semiconductor substrate. The method comprises: (a) forming a dielectric structure on the semiconductor substrate; (b) etching a portion of an electrically conducting region disposed to a side of the dielectric structure, wherein the electrically conducting region is etched at a faster rate than the dielectric structure; and (c) depositing a conductive material on the etched electrically conducting region.
Another embodiment of the invention is directed to a method for removing surface contamination on a semiconductor substrate. The method comprises: (a) forming a field effect transistor on a semiconductor substrate, wherein the field effect transistor has a gate electrode, a source region, and a drain region; (b) forming a dielectric structure on the gate electrode and the source region; (c) reflowing the dielectric structure; (d) etching a portion of the electrically conducting region disposed to a side of the reflowed dielectric structure, wherein the electrically conducting region is etched at a faster rate than the dielectric structure; (e) forming a barrier layer for a Schottky diode on the etched electrically conducting region; and (f) depositing a conductive layer on the barrier layer.
Other embodiments of the invention relate to products made by such methods.
These and other embodiments of the invention are described in further detail with reference to the Figures and the detailed description.